XCZU9EG-1FFVB1156I 订货13632767652黄小姐微信同号
Xilinx® UltraScale architecture comprises high-performance FPGA and MPSoC families that address a vast spectrum of system requirements with a focus on lowering total power c***umption through numerous innovative technological advancements. Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost. Kintex UltraScale+ FPGAs: Based on the UltraScale architecture, these devices h***e increased performance and on-chip UltraRAM memory to reduce BOM cost, providing the ideal mix of high-performance peripherals and cost-effective system implementation. In addition, Kintex UltraScale+ FPGAs h***e numerous power opti*** that deliver the optimal balance between the required system performance and the ***allest power envelope. Virtex® UltraScale FPGAs: The industry's most capable high-performance FPGAs enabled using both monolithic and next-generation SSI technology to achieve the highest system capacity, bandwidth, and performance. Variants of the Virtex UltraScale family are optimized to address key market and application requirements through integration of various system-level functi***, delivering unprecedented embedded memory and serial connectivity capabilities. Virtex UltraScale+ FPGAs: Based on the UltraScale architecture, these devices h***e the highest transceiver bandwidth, highest DSP count, and highest on-chip memory ***ailable in the industry for the ultimate in system performance. In addition, Virtex UltraScale+ FPGAs also provide numerous power opti*** that deliver the optimal balance between the required system performance and the ***allest power envelope. Zynq® UltraScale+ MPSoCs: Combine the ARM® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the ARM Cortex-R5 real-time processor and the UltraScale architecture to create the industry’s first All Programmable MPSoCs. With next-generation programmable engines, security, safety, reliability, and scalability from 32 to 64 bits, the Zynq UltraScale+ MPSoCs provide unprecedented power s***ings, processing, programmable acceleration, I/O, and memory bandwidth ideal for applicati*** that require heterogeneous processing.
XCZU9EG-1FFVB1156I Key Features
UltraScale+ MPSoCs are built around a feature-rich quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processing system (PS). In addition to the 32-bit/64-bit application processing unit (APU) and 32-bit real-time processing unit (RPU), the PS contains a dedicated ARM Mali™-400 MP2 graphics processing unit (GPU). To support the processors' functionality, a number of peripherals with dedicated functi*** are included in the PS. For interfacing to external memories for data or configuration storage, the PS includes a multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller and a Quad SPI controller. In addition to interfacing to external memories, the processing units also contain their level 1 and/or level 2 caches and 256KB of on-chip memory. For high-speed interfacing, the PS includes 4 channels of tran***it (TX) and receive (RX) pairs of transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can interface to the high-speed peripheral blocks to support PCIe Gen2 root complex or end point in x1, x2, or x4 configurati***; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and up to two lanes of Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can also interface to components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII). For general connectivity, the PS includes: a pair of USB 2.0 controllers, which can be configured as host, device, or On-The-Go (OTG); an I2C controller; a UART; and a CAN2.0B controller that conforms to ISO11898-1. There are also four triple speed Ethernet MACs and 128 bits of GPIO, of which 78 bits are ***ailable through the MIO and 96 through the EMIO. High-bandwidth connectivity based on the ARM AMBA® AXI4 protocol connects the processing units with the peripherals and provides interface between the PS and the programmable logic (PL). For additional information, go to: DS891, Zynq UltraScale+ MPSoC Overview.
Xilinx®超薄架构包括高性能FPGA和MPSoC系列，它们解决了大量的系统需求，***在于通过许多创新的技术进步降低总功耗。KNTEX®超薄FPGA：高性能FPGAs专注于价格/性能，同时使用单片和下一代堆叠硅互连（SSI）技术。高DSP和块RAM的逻辑比和下一代收发器，结合低成本封装，使能力和成本的***佳混合。KiTeX SuxCale+FPGA：基于超薄架构，这些设备增加了性能和片上ULTRARAM内存，以减少BOM成本，提供了高性能外围设备和成本效益的系统实现的理想组合。此外，KiTeX Upjale+FPGA具有多种功率选项，提供所需系统性能与***小功率包络之间的***佳平衡。ViTeX®超薄FPGA：业界***有能力的高性能FPGA使用单片和下一代SSI技术实现***高的系统容量、带宽和性能。ViTEX UpjalCe家族的变体被优化以通过整合各种系统级功能来解决关键市场和应用需求，提供***的嵌入式存储器和串行连接能力。ViTEX超高+FPGA：基于超薄架构，这些设备具有***高的收发器带宽、***高DSP计数和***高的片上存储器，用于工业系统的***终性能。此外，ViTEX超高速+FPGA还提供了多种功率选项，提供了所需系统性能与***小功率包络之间的***佳平衡。ZYNQ®超薄+ MPSOCS：结合ARM®V8基于Or***e®-A53高性能节能64位应用处理器与ARM CORTEX-R5实时处理器和超薄架构，以创建业界***个全可编程MPSoC。随着下一代可编程引擎、安全性、安全性、可靠性和可扩展性从32位增加到64位，ZYNQ UpjCale+MPSOCS提供了***的功率节省、处理、可编程加速、I/O和存储器带宽，这对于需要异构处理的应用来说是理想的。G.
XCZU9EG-1FFVB1156I 关键特征
在一个功能丰富的四核臂CORTEX-A53和双核ARCORTEX-R5处理系统（PS）的基础上构建了超小型+MPSOCS。除了32位/ 64位应用处理单元（APU）和32位实时处理单元（RPU）外，PS包含专用ARM MARIμ- 400 MP2图形处理单元（GPU）。为了支持处理器的功能，在PS中包括若干具有专用功能的外设，用于与外部存储器接口以进行数据或配置存储，PS包括多协议动态存储器控制器、DMA控制器、NAND控制器、SD/EMMC CONT。辊和四SPI控制器。除了连接到外部存储器之外，处理单元还包含1级和/或级2高速缓存和256KB片上存储器。对于高速接口，PS包括4个传输信道（TX）和接收（RX）对收发器，称为PS-GTR收发器，支持高达60Gb/s的数据速率。这些收发器可以与高速外围模块接口，以支持PCIe GE2根复合物或端点。X1，X2，或X4配置；串行ATA（SATA）在1.5 Gb/s，3.0Gb/s，或60Gb/s数据速率；以及在1.62Gb/s，2.7Gb/s，或5.4Gb/s数据速率的两个显示端口上。PS-GTR收发器还可以与USB 3和串行千兆媒体***接口（SGMII）上的组件接口。对于一般的连接性，PS包括：一对USB 2控制器，其可以配置为主机、设备或GO（OTG）；I2C控制器；UART；以及符合ISO11898-1的CAN2.0B控制器。也有四个三速以太网MAC和128位GPIO，其中78位可通过MIO和96通过EMIO。基于ARM AMBA®AXI4协议的高带宽连接将处理单元与外围设备连接，并提供PS和可编程逻辑（PL）之间的接口。有关附加信息，请访问：DS891、ZYNQ UpjalC+MPSoC概述。
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