X***VSX55-10FF1148I 订货13632767652 黄云艳
X***VSX55-10FF1148I 中英文资料
Combining Advanced Silicon Modular Block (A***BL) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families—LX, FX, and SX—offering multiple feature choices and combinati*** to address all complex applicati***. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology.
X***VSX55-10FF1148IKey Features
- Virtex-4 SX: High-performance solution for digital signal processing (DSP) applicati***
- Xesium™ Clock Technology
- Digital clock manager (DCM) blocks
- Additional phase-matched clock dividers (PMCD)
- Differential global clocks
- XtremeDSP™ Slice
- 18 x 18, two’s complement, signed Multiplier
- Optional pipeline stages
- Built-in Accumulator (48-bit) and Adder/Subtracter
- ***art RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks · Optional pipeline stages · Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.
- SelectIO™ Technology
- 1.5V to 3.3V I/O operation
- Built-in ChipSync™ source-synchronous technology
- Digitally controlled impedance (DCI) active termination
- Fine grained I/O banking (configuration in one bank)
- Flexible Logic Resources
- Secure Chip AES Bitstream Encryption
- 90 nm Copper CMOS Process
- 1.2V Core Voltage
- Flip-Chip Packaging including Pb-Free Package Choices
结合***的硅模块化模块（ASBML）架构和各种灵活的特性，VilTeX®- 4系列从Xilinx极大地增强了可编程逻辑设计能力，使其成为ASIC技术的有力替代品。VITEX-4 FPGA包括三个平台家族LX、FX和SX，提供多个特征选择和组合，以解决所有复杂的应用。广泛的VerTeX-4 FPGA硬IP核心块包括PowerPC®处理器（具有新的APU接口）、三模式以太网MAC、622 Mb/s到6.5 Gb/s串行收发器、专用DSP片、高速时钟管理电路和源同步接口块。基本的ViReX-4 FPGA积木是在流行的ViTeX、ViTeX-E、ViTEX II、ViTEX II PRO和ViTEX II PRO X系列产品中发现的，因此上一代的设计是向上兼容的。使用300毫米（12英寸）晶片技术在******的90纳米铜工艺上生产ViTEX-4器件。
关键特征
VIETEX-4 SX:数字信号处理（DSP）应用的高性能解决方案
氙气钟技术
数字时钟管理器（DCM）模块
附加相位匹配时钟分频器（PMCD）
差分全局时钟
X射线切片
18×18，两补，有符号乘法器
可选管道级
内置累加器（48位）和加法器/减法器
智能RAM存储器层次结构
分布式随机存取存储器
双端口18位RAM块·可选流水线级·可选的可编程FIFO逻辑自动将RAM信号重新映射为FIFO信号
高速内存接口支持DDR和DDR-2 SDRAM、QDR-Ⅱ和RLFRADE-II。
选择技术
1.5V至3.3V I/O操作
内置CHIP-Syc源同步技术
数字控制阻抗（DCI）主动端接
细粒度I/O***（一个***的配置）
柔性逻辑资源
安全芯片AES比特流加密
90 nm铜CMOS工艺
1.2V铁心电压
包括无铅封装选择的倒装芯片封装
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