***320DM642AGDKS7EP

订货13632767652 黄云艳

***320DM642AGDKS7EP

中英文资料

C6X DSP（包括***3DM62-EP设备）是C6000 DSP平台上***高性能的定点DSP产生。DM642设备是基于德克萨斯仪器（TI）开发的第二代高性能、***的速度超长指令字（VLIW）架构（VeliCiTi 2），使这些DSP成为数字媒体应用的***佳选择。C64是C6000 DSP平台的代码兼容成员。

DM642设备以每秒720 MHz的时钟速率提供高达每秒57亿6000万条指令（MIPS），从而为高性能DSP编程挑战提供了成本效益高的解决方案。DM642 DSP具有高速控制器的操作灵活性和阵列处理器的数字能力。C64 X DSP核心处理器具有32位字长的64个通用寄存器和八个高度***的功能单元，32位结果的两个乘法器和六个算术逻辑单元（ALU）-具有速度2扩展。八个功能单元中的RelosiTi 2扩展包括在视频和成像应用中加速性能的新指令，并扩展了速度架构的并行性。DM642每周期可产生四个16位乘法累加（MACS），每秒钟总共有28亿8000万个MAC（MMACS），或每周期八个8位MACS，总共5760 MMACS。DM642 DSP还具有特定于应用的硬件逻辑、片上存储器和类似于其他C6000 DSP平台设备的附加的片上外设。

DM642使用基于两级高速缓存的体系结构，并具有强大且多样化的外围设备集。1级程序缓存（L1P）是一个128 k比特的直接映射缓存，1级数据缓存（L1D）是一个128 k比特的2路集合关联缓存。2级存储器/高速缓存（L2）由在程序和数据空间之间共享的2兆位存储器空间组成。L2内存可以被配置为映射内存、缓存或两者的组合。外围设备包括：三个可配置视频端口；10/100 Mbps以太网MAC（EMAC）；管理数据输入/输出（MIDO）模块；VCXO内插控制端口（VIC）；一个多通道缓冲音频串行端口（McASP0）；一个集成电路（I2C）总线模块；两个多通道。缓冲串行端口（MCBSP）；三个32位通用定时器；用户可配置的16位或32位主机端口接口（HPI16/HPI32）；外围组件互连（PCI）；具有可编程中断/事件生成模式的16针通用输入/输出端口（GP0）；以及64位G。Louess外部存储器接口（EMIFA），它能够连接到同步和异步存储器和外围设备。

DM642设备具有三个可配置的视频端口外围设备（VP0、VP1和VP2）。这些视频端口外设提供普通视频***器和编码器设备的无缝接口。DM642视频端口外围设备支持多个分辨率和视频标准（例如CCI601、ITU-BT.665、BT.1120、***PTE 125M、260M、244M和266M）。

这三个视频端口外设是可配置的，可以支持视频捕获和/或视频显示模式。每个视频端口由两个通道组成，A和B具有5120字节捕获/显示缓冲器，在两个通道之间是可分离的。

有关视频端口外设的更多细节，请参阅TMS3C64 X DSP视频端口/VCXO内插控制（VIC）端口参考指南（文献号SPRU629）。

The C64x DSPs (including the ***320DM642-EP device) are the highest-performance fixed-point DSP generation in the C6000 DSP platform. The DM642 device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applicati***. The C64x is a code-compatible member of the C6000 DSP platform.

With performance of up to 5760 million instructi*** per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective soluti*** to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2 extensi***. The VelociTI.2 extensi*** in the eight functional units include new instructi*** to accelerate the performance in video and imaging applicati*** and extend the paralleli*** of the VelociTI architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific ha***are logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) c***ists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinati*** of the two. The peripheral set includes: three configurable video ports; a 10/100 Mbps Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resoluti*** and video standa*** (e.g., CCIR601, ITU-BT.656, BT.1120, ***PTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port c***ists of two channels — A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

本周热卖型号推荐：
X***VLX15-10FFG668I 100 XILINX 17+
X***VLX60-10FF1148I 2106 XILINX 17+
X***VLX100-11FF1148I 528 XILINX 17+
X***VSX55-10FF1148I 12 XILINX 17+
XQ7K325T-1RF900M 10 XILINX 17+
XC7VX690T-2FFG1157I 30 XILINX 17+
XC7VX690T-2FFG1761I 80 XILINX 17+
XC7VX690T-2FFG1930I 10 XILINX 18+
XC6VSX475T-2FFG1156E 50 XILINX 17+
XC6VLX240T-2FFG1156I 30 XILINX 17+
XC5VFX100T-2FFG1136I 100 XILINX 17+
XC3S500E-4PQ208I 130 XILINX 17+
XA6SLX45-2CSG324Q 59 XILINX 17+
X***VSX55-11FFG1148I 109 XILINX 17+
XC3S50AN-4TQG144I 30 XILINX 17+
XQ4028EX-4CB228M 20 XILINX
XQ4028EX-4CB228M 20 XILINX 10+
XC5VLX220-2FFG1760I 21 XILINX 17+
XC3S700AN-4FGG484I 44 XILINX 16+
XA6SLX75-2CSG484I 13 XILINX 17+
XC6VSX475T-1FFG1156I 180 XILINX 17+
XCKU095-2FFVA1156I 8 XILINX 17+
X***062XL-3HQ240C 170 XILINX
XC5VLX50T-1FFG665I 30 XILINX 16+
XA6SLX75-2CSG484Q 8 XILINX 17+
XC5VSX50T-2FFG1136I 120 XILINX 17+
XC5VFX130T-2FF1738I 30 XILINX 17+