The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applicati***. The thirteen-member family delivers expanded densities ranging from to 147,443 logic cells, with half the power c***umption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIOTM technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration opti***, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, c***umer-oriented DSP designs, and cost-sensitive embedded applicati***. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and ha***are components that enable designers to focus on innovation as soon as their development cycle begins.
Spartan-6 Family: Spartan-6 LX FPGA: Logic optimized Spartan-6 LXT FPGA: High-speed serial connectivity Designed for low cost Multiple efficient integrated blocks Optimized selection of I/O standa*** Staggered pads High-volume plastic wire-bonded packages Low static and dynamic power 45 nm process optimized for cost and low power Hibernate power-down mode for zero power Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement Lower-power 1.0V core voltage (LX FPGAs, -1L only) High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades) Multi-voltage, multi-standard SelectIOTM interface banks to 1,080 Mb/s data transfer rate per differential I/O Selectable output drive, 24 mA per pin to 1.2V I/O standa*** and protocols Low-cost HSTL and SSTL memory interfaces Hot swap compliance Adjustable I/O slew rates to improve signal integrity High-speed GTP serial transceivers in the LXT FPGAs to 3.2 Gb/s High-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI Integrated Endpoint block for PCI Express designs (LXT) Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification. Efficient DSP48A1 slices High-performance arithmetic and signal processing Fast x 18 multiplier and 48-bit accumulator Pipelining and cascading capability Pre-adder to assist filter applicati*** Integrated Memory Controller blocks DDR, DDR2, DDR3, and LPDDR support Data rates to 800 Mb/s (12.8 Gb/s peak bandwidth) Multi-port bus structure with independent FIFO to reduce design timing issues Abundant logic resources with increased logic capacity Optional shift register or distributed RAM support Efficient 6-input LUTs improve performance and minimize power LUT with dual flip-flops for pipeline centric applicati*** Block RAM with a wide range of granularity Fast block RAM with byte write enable 18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs Clock Management Tile (CMT) for enhanced performance Low noise, flexible clocking Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion Phase-Locked Loops (PLLs) for low-jitter clocking Frequency synthesis with simultaneous multiplication, division, and phase shifting Sixteen low-skew global clock networks Simplified configuration, supports low-cost standa*** 2-pin auto-detect configuration Broad third-party SPI (up to x4) and NOR flash support Feature rich Xilinx Platform Flash with JTAG MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection Enhanced security for design protection Unique Device DNA identifier for design authentication AES bitstream encryption in the larger devices Faster embedded processing with enhanced, low cost, MicroBlazeTM soft processor Industry-leading IP and reference designs
© 20092011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Configurable Logic Blocks (CLBs) Device Logic Cells(1) Slices(2) Max Flip-Flops Distributed RAM (Kb) DSP48A1 Slices(3) Block RAM Blocks Kb(4) CMTs(5) Max (Kb) Memory Endpoint Maximum Total Max Controller Blocks for GTP I/O User Blocks PCI Express Transceivers Banks I/O (Max)(6)
Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops. Each DSP48A1 slice contains x 18 multiplier, an adder, and an accumulator. Block RAMs are fundamentally Kb in size. Each block can also be used as two independent 9 Kb blocks. Each CMT contains two DCMs and one PLL. Memory Controller Blocks are not supported in the -3N speed grade.
Spartan-6 FPGA package combinati*** with the ***ailable I/Os and GTP transceivers per package are shown in Table 2. Due to the transceivers, the LX and LXT pinouts are not compatible. Table 2: Spartan-6 Device-Package Combinati*** and Maximum ***ailable I/Os
Package Body Size (mm) Pitch (mm) Device 8x8 0.5
Notes: 1. There is no memory controller on the devices in these packages. 2. Memory controller block support x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the XC6SLX4. 3. These devices are ***ailable in both Pb and Pb-free (additional G) packages as standard ordering opti***. 4. These packages support two of the four memory controllers in the XC6SLX100T, XC6SLX150, and XC6SLX150T devices.
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3 Mb and 33 Mb depending on device size and user-design implementation opti***. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for loading configuration are ***ailable. Bit-serial configurati*** can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or sl***e serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurati***, master SelectMAP mode generates the CCLK signal while sl***e SelectMAP mode receives the CCLK signal for the 8- and 16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an external clock, which can be faster or more precise than the internal clock. The ***ailable JTAG pins use boundary-scan protocols to load bit-serial configuration data.