BentlyNevada 330180-50-05
降低SER的方法分为几类，包括工艺变更(埋层、三层阱等)、电路强化(阻性反馈、在存储节点上设置较高的电容、较高的驱动电压等)、设计强化(冗余等)和系统级变更。
系统级对策
在系统级上，可根据读操作来进行误差检测和校正，并通过使SRAM的延迟(等待时间)略有增加的方法来***SRAM的SER上升。这样可对数据进行一位误差校正并报告多位误差。还可以借助系统和存储器架构设计来实现某些改进。存储器拓扑位图可以按照使一个实际的多位事件在一个字节中导致一个多位或一位误差的方式来构成。ECC在校正一位误差方面是非常有效的，但采用它同时也意味着芯片面积将至少增加20%。
器件工艺/封装级对策
从器件设计的角度来看，***SER并增强器件对SER的抵御能力的途径之一是增加存储单元中所存储的临界电荷量。人们注意到，PMOS门限电压可减少存储单元的***时间，这间接起到了提高SER抵御能力的作用。另外，在发生软误差期间所产生的电荷可利用埋入式结点(三层阱架构)来驱散，以增加远离***性区的再结合。这将生成一个与NMOS耗尽层方向相反的电场，并强制电荷进入衬底。然而，这种三层阱架构只是在辐射发生于NMOS区域中的时候才能起到一定的补救作用。
结语
随着加工工艺尺寸的日益缩小，“软”误差对存储器件的影响已经从原先的“无关紧要”演变成为系统设计中需要加以认真考虑的重要事项。赛普拉斯等SRAM售主已经在工艺开发和产品设计当中采取了相应的对策，以求***大限度地降低器件对SER的敏感度，并由此将SRAM的应用范围扩展到远远小于90nm的工艺几何尺寸。凭借在系统设计和产品设计水平的正确对策，SRAM仍将是多代工艺中一种可行的存储器解决方案
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