ABB DCS AC800M模块 CI867K01 CI857K01
ABB DCS AC800M模块 CI867K01 CI857K01
ABB DCS AC800M模块 CI867K01 CI857K01
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ADSP-TS201处理器有一个专用的SDRAM接口．可以实现与标准SDRAM6Mb，64Mb，128Mb．256Mb．512Mb的无缝连接。支持1024-，512-，256字的页面长度，通过对SDRCON寄存器的编程可实现页面长度的选择。同时SDRAM占用TS201的外部存储空间地址，通过设置／MSSD3～0来确定SDRAM的地址空间范围。
本设计选用的SDRAM是HY57V561620B，页面长度为512字，将两片SDRAM拼接成32位的总线宽度，实现与TS201的无缝接口。根据不同的总线宽度，TS201的地址总线与SDRAM的连接有所不同。
(1)对于32位数据总线其连接方式如下：
SDRAM地址Bit9～0与TS201ADDR9～0相连；
SDRAM地址Bitl0与TS201的SDA10管脚相连；
SDRAM地址Bitl5～11与TS201ADDRl5～11相连。
(2)对于64位数据总线，连接方式如下：
SDRAM地址Bit9～0与TS201ADDRl0～1相连，TS201ADDR0悬空；
SDRAM地址Bitl0与TS201的SDAl0管脚相连；
SDRAM地址Bitl4～11与TS201ADDRl5～12相连。
另外对于标准的SDRAM(3．3V)，TS201的地址线ADDRl5∽11都可以作为BANK的选择线。对于低功率的SDRAM(2．5V)，只有ADDRl5～14可以作为BANK的选择线。因此在进行接VI设计时一定要注意所选择SDRAM的电参数。
4．2ADSP-T$201与FPGA接口
本文设计的系统需要将FPGA连接在TS201的外部总线上，采用DMA中断，通过总线的方式从FPGA的***RAM(乒乓存储)中读取数字下变频后的I，Q两路数据，其连接方式如图3所示。
TS201和FPGA接口
其中MS0，MS1是片选信号，RD和WRL分别是读和写信号。在一个PRF周期内FPGA进行数字下变频，将I，Q数据存储到SRAM中，然后向TS201发出DMA请求，TS201将SRAM的数据采用流水线协议通过总线读入片内RAM中，进行后续的处理。再将处理完的数据以总线方式写入到FPGA内部RAM中，以便进行在线仿真或者进行后续的输出。
5结语
本文主要结合ADI公司的高性能ADSP-TS201的结构特点，讨论了在系统设计的过程中应该***注意的几个问题和ADSP-TS201的外部接口技术，并给出了其与SDRAM，FPGA的连接实例，对基于TigerSHARC系列DSP的应用设计具有实用的参考价值。
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