Key Features
﹡ VDD : 2.5V &plu***n;0.2V, VDDQ : 2.5V &plu***n; 0.2V for DDR266, 333
VDD: 2.6V &plu***n;0.1V, VDDQ : 2.6V &plu***n; 0.1V for DDR400
﹡ Double-data-rate architecture; two data transfers per clock cycle
﹡ Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
﹡ Four banks operation
﹡ Differential clock inputs(CK and CK
﹡ DLL aligns DQ and DQS transition with CK transition
﹡ MRS cycle with address key programs
-. Read latency : DDR266(2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interle***e)
﹡ All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
﹡ Data I/O transacti*** on both edges of data strobe
﹡Edge aligned data output, center aligned data input
﹡ LDM,UDM for write masking only (x16)
﹡ DM for write masking only (x4, x8)
﹡ Auto & Self refresh
﹡ 7.8us refresh interval(8K/64ms refresh)
﹡ Maximum burst refresh cycle : 8
﹡ 66pin TSOP II Lead-Free & Halogen-Free package
﹡ RoHS compliant
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